1. Field
Example embodiments relate to a semiconductor memory device, and for example, to a semiconductor memory device including a recessed control gate electrode.
2. Description of Related Art
With recent trends toward smaller and faster devices in the semiconductor industry, semiconductor memory devices have become more highly integrated and faster in operation. Accordingly, three-dimensional (3D) semiconductor memory devices have been introduced as substitutes for conventional planar semiconductor memory devices. For example, conventional 3D semiconductor memory devices may include a recessed control gate electrode trenched into a semiconductor substrate.
If compared with conventional planar semiconductor memory devices, conventional 3D nonvolatile semiconductor memory devices have a higher channel area and a higher operating current. The higher operating current results in an increase in the speed of conventional 3D semiconductor memory devices. However, unit cells of conventional 3D semiconductor memory devices occupy larger areas and operate in one bit. Accordingly, a limitation in increasing the integration density of conventional 3D semiconductor memory devices exists.
Source and drain regions of conventional 3D semiconductor memory devices occupy larger areas. For example, negative AND (NAND)-type semiconductor memory devices that are superior in integration density are configured such that source and drain regions are alternately arranged, thereby occupying larger areas and limiting the integration density. The distribution of electric field density in conventional 3D semiconductor memory devices is not uniform, thereby decreasing reliability in program and erase operations.